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[DIR]adms/2022-07-16 11:04 -
[DIR]atlc/2022-07-16 11:04 -
[DIR]boolean/2022-07-16 11:04 -
[DIR]cascade/2022-07-16 11:04 -
[DIR]cgi-wcalc/2022-07-16 11:04 -
[DIR]covered/2022-07-16 11:04 -
[DIR]CVS/2022-07-16 11:04 -
[DIR]dinotrace-mode/2022-07-16 11:04 -
[DIR]dinotrace/2022-07-16 11:04 -
[DIR]diylc/2022-07-16 11:04 -
[DIR]eagle/2022-07-16 11:04 -
[DIR]electric/2022-07-16 11:04 -
[DIR]fastcap/2022-07-16 11:04 -
[DIR]fasthenry/2022-07-16 11:04 -
[DIR]felt/2022-07-16 11:04 -
[DIR]freehdl/2022-07-16 11:04 -
[DIR]gdsreader/2022-07-16 11:04 -
[DIR]geda/2022-07-16 11:04 -
[DIR]gerbv/2022-07-16 11:04 -
[DIR]ghdl/2022-07-16 11:04 -
[DIR]gnetman/2022-07-16 11:04 -
[DIR]gnucap/2022-07-16 11:04 -
[DIR]gplcver/2022-07-16 11:04 -
[DIR]gsmc/2022-07-16 11:04 -
[DIR]gtk1-wcalc/2022-07-16 11:04 -
[DIR]gtk2-wcalc/2022-07-16 11:04 -
[DIR]gtkwave/2022-07-16 11:04 -
[DIR]iverilog/2022-07-16 11:04 -
[DIR]kicad-doc/2022-07-16 11:04 -
[DIR]kicad-footprints/2022-07-16 11:04 -
[DIR]kicad-i18n/2022-07-16 11:04 -
[DIR]kicad-packages3d/2022-07-16 11:04 -
[DIR]kicad-symbols/2022-07-16 11:04 -
[DIR]kicad-templates/2022-07-16 11:04 -
[DIR]kicad/2022-07-16 11:04 -
[DIR]klayout/2022-07-16 11:04 -
[DIR]librecad/2022-07-16 11:04 -
[DIR]libredwg/2022-07-16 11:04 -
[DIR]libwcalc/2022-07-16 11:04 -
[DIR]magic/2022-07-16 11:04 -
[DIR]mcalc/2022-07-16 11:04 -
[DIR]mex-wcalc/2022-07-16 11:04 -
[DIR]mpac/2022-07-16 11:04 -
[DIR]MyHDL-gplcver/2022-07-16 11:04 -
[DIR]MyHDL-iverilog/2022-07-16 11:04 -
[DIR]nelma/2022-07-16 11:04 -
[DIR]ng-spice/2022-07-16 11:04 -
[DIR]ntesla/2022-07-16 11:04 -
[DIR]oce/2022-07-16 11:04 -
[DIR]openscad/2022-07-16 11:04 -
[DIR]p5-gds2/2022-07-16 11:04 -
[DIR]pcb/2022-07-16 11:04 -
[DIR]py-gds/2022-07-16 11:04 -
[DIR]py-gdscad/2022-07-16 11:04 -
[DIR]py-MyHDL/2022-07-16 11:04 -
[DIR]py-PyRTL/2022-07-16 11:04 -
[DIR]py-simpy/2022-07-16 11:04 -
[DIR]qcad-partlibrary/2022-07-16 11:04 -
[DIR]qcad/2022-07-16 11:04 -
[DIR]sci-wcalc/2022-07-16 11:04 -
[DIR]solvespace/2022-07-16 11:04 -
[DIR]spice/2022-07-16 11:04 -
[DIR]spiceprm/2022-07-16 11:04 -
[DIR]stdio-wcalc/2022-07-16 11:04 -
[DIR]tkgate/2022-07-16 11:04 -
[DIR]tnt-mmtl/2022-07-16 11:04 -
[DIR]transcalc/2022-07-16 11:04 -
[DIR]verilator/2022-07-16 11:04 -
[DIR]verilog-mode/2022-07-16 11:04 -
[DIR]veriwell/2022-07-16 11:04 -
[DIR]wcalc-docs/2022-07-16 11:04 -
[DIR]wcalc/2022-07-16 11:04 -
[DIR]xchiplogo/2022-07-16 11:04 -
[DIR]xcircuit/2021-09-28 18:43 -
[   ]Makefile2021-04-12 14:17 1.4K