$NetBSD: patch-as,v 1.1 2010/01/17 08:00:47 dholland Exp $

Patch out gcc language extensions that are no longer supported.

--- esame.c~	2001-02-10 14:41:55.000000000 +0000
+++ esame.c
@@ -945,8 +945,8 @@ U32     i2;                             
 
     RIL(inst, execflag, regs, r1, opcd, i2);
 
-    GR_A(r1, regs) = ((!execflag ? (regs->psw.IA - 6) : regs->ET)
-                                 + 2*(S32)i2) & ADDRESS_MAXWRAP(regs);
+    GR_Ax(r1, regs, ((!execflag ? (regs->psw.IA - 6) : regs->ET)
+                                 + 2*(S32)i2) & ADDRESS_MAXWRAP(regs));
 }
 
 
@@ -1440,7 +1440,7 @@ int     i,j;                            
     j = (r3 & 1) ? (S64)regs->GR_G(r3) : (S64)regs->GR_G(r3+1);
 
     /* Add the increment value to the R1 register */
-    (S64)regs->GR_G(r1) += i;
+    regs->GR_G(r1) = (S64)regs->GR_G(r1) + i;
 
     /* Branch if result compares high */
     if ( (S64)regs->GR_G(r1) > j )
@@ -1468,7 +1468,7 @@ int     i,j;                            
     j = (r3 & 1) ? (S64)regs->GR_G(r3) : (S64)regs->GR_G(r3+1);
 
     /* Add the increment value to the R1 register */
-    (S64)regs->GR_G(r1) += i;
+    regs->GR_G(r1) = (S64)regs->GR_G(r1) + i;
 
     /* Branch if result compares low or equal */
     if ( (S64)regs->GR_G(r1) <= j )
@@ -1497,7 +1497,7 @@ S64     i, j;                           
     j = (r3 & 1) ? (S64)regs->GR_G(r3) : (S64)regs->GR_G(r3+1);
 
     /* Add the increment value to the R1 register */
-    (S64)regs->GR_G(r1) += i;
+    regs->GR_G(r1) = (S64)regs->GR_G(r1) + i;
 
     /* Branch if result compares high */
     if ( (S64)regs->GR_G(r1) > j )
@@ -1525,7 +1525,7 @@ S64     i, j;                           
     j = (r3 & 1) ? (S64)regs->GR_G(r3) : (S64)regs->GR_G(r3+1);
 
     /* Add the increment value to the R1 register */
-    (S64)regs->GR_G(r1) += i;
+    regs->GR_G(r1) = (S64)regs->GR_G(r1) + i;
 
     /* Branch if result compares low or equal */
     if ( (S64)regs->GR_G(r1) <= j )
@@ -1586,7 +1586,7 @@ U64     n;                              
        the physical CPU on a spinlock */
     if(regs->psw.cc && sysblk.numcpu > 1 && sysblk.brdcstncpu == 0)
         usleep(1L);
-#endif MAX_CPU_ENGINES > 1
+#endif /* MAX_CPU_ENGINES > 1 */
 
 #if defined(_FEATURE_ZSIE)
     if(regs->sie_state && (regs->siebk->ic[0] & SIE_IC0_CS1))
@@ -1652,7 +1652,7 @@ U64     n1, n2;                         
        the physical CPU on a spinlock */
     if(regs->psw.cc && sysblk.numcpu > 1 && sysblk.brdcstncpu == 0)
         usleep(1L);
-#endif MAX_CPU_ENGINES > 1
+#endif /* MAX_CPU_ENGINES > 1 */
 
 #if defined(_FEATURE_ZSIE)
     if(regs->sie_state && (regs->siebk->ic[0] & SIE_IC0_CDS1))
@@ -2071,7 +2071,7 @@ int     r1, r2;                         
     }
 
     /* Load positive value of second operand and set cc */
-    (S64)regs->GR_G(r1) = (S64)regs->GR_G(r2) < 0 ?
+    regs->GR_G(r1) = (S64)regs->GR_G(r2) < 0 ?
                             -((S64)regs->GR_G(r2)) :
                             (S64)regs->GR_G(r2);
 
@@ -2089,9 +2089,9 @@ int     r1, r2;                         
     RRE(inst, execflag, regs, r1, r2);
 
     /* Load positive value of second operand and set cc */
-    (S64)regs->GR_G(r1) = (S32)regs->GR_L(r2) < 0 ?
+    regs->GR_G(r1) = (S64)((S32)regs->GR_L(r2) < 0 ?
                             -((S32)regs->GR_L(r2)) :
-                            (S32)regs->GR_L(r2);
+                            (S32)regs->GR_L(r2));
 
     regs->psw.cc = (S64)regs->GR_G(r1) == 0 ? 0 : 2;
 }
@@ -2107,7 +2107,7 @@ int     r1, r2;                         
     RRE(inst, execflag, regs, r1, r2);
 
     /* Load negative value of second operand and set cc */
-    (S64)regs->GR_G(r1) = (S64)regs->GR_G(r2) > 0 ?
+    regs->GR_G(r1) = (S64)regs->GR_G(r2) > 0 ?
                             -((S64)regs->GR_G(r2)) :
                             (S64)regs->GR_G(r2);
 
@@ -2125,9 +2125,9 @@ int     r1, r2;                         
     RRE(inst, execflag, regs, r1, r2);
 
     /* Load negative value of second operand and set cc */
-    (S64)regs->GR_G(r1) = (S32)regs->GR_L(r2) > 0 ?
+    regs->GR_G(r1) = (S64) ((S32)regs->GR_L(r2) > 0 ?
                             -((S32)regs->GR_L(r2)) :
-                            (S32)regs->GR_L(r2);
+                            (S32)regs->GR_L(r2));
 
     regs->psw.cc = (S64)regs->GR_G(r1) == 0 ? 0 : 1;
 }
@@ -2160,7 +2160,7 @@ int     r1, r2;                         
     RRE(inst, execflag, regs, r1, r2);
 
     /* Copy second operand and set condition code */
-    (S64)regs->GR_G(r1) = (S32)regs->GR_L(r2);
+    regs->GR_G(r1) = (S64)(S32)regs->GR_L(r2);
 
     regs->psw.cc = (S64)regs->GR_G(r1) < 0 ? 1 :
                    (S64)regs->GR_G(r1) > 0 ? 2 : 0;
@@ -2187,7 +2187,7 @@ int     r1, r2;                         
     }
 
     /* Load complement of second operand and set condition code */
-    (S64)regs->GR_G(r1) = -((S64)regs->GR_G(r2));
+    regs->GR_G(r1) = -((S64)regs->GR_G(r2));
 
     regs->psw.cc = (S64)regs->GR_G(r1) < 0 ? 1 :
                    (S64)regs->GR_G(r1) > 0 ? 2 : 0;
@@ -2204,7 +2204,7 @@ int     r1, r2;                         
     RRE(inst, execflag, regs, r1, r2);
 
     /* Load complement of second operand and set condition code */
-    (S64)regs->GR_G(r1) = -((S32)regs->GR_L(r2));
+    regs->GR_G(r1) = (S64) -((S32)regs->GR_L(r2));
 
     regs->psw.cc = (S64)regs->GR_G(r1) < 0 ? 1 :
                    (S64)regs->GR_G(r1) > 0 ? 2 : 0;
@@ -2526,9 +2526,9 @@ U64     n;                              
     regs->GR_G(r1) = regs->GR_G(r3);
 
     /* Shift the signed value of the R1 register */
-    (S64)regs->GR_G(r1) = n > 62 ?
+    regs->GR_G(r1) = (S64) (n > 62 ?
                     ((S64)regs->GR_G(r1) < 0 ? -1 : 0) :
-                    (S64)regs->GR_G(r1) >> n;
+                    (S64)regs->GR_G(r1) >> n);
 
     /* Set the condition code */
     regs->psw.cc = (S64)regs->GR_G(r1) > 0 ? 2 :
@@ -2552,7 +2552,7 @@ U32     n;                              
     n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
 
     /* Multiply signed operands ignoring overflow */
-    (S64)regs->GR_G(r1) *= (S32)n;
+    regs->GR_G(r1) = (S64)regs->GR_G(r1) * (S32)n;
 
 }
 
@@ -2573,7 +2573,7 @@ U64     n;                              
     n = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
 
     /* Multiply signed operands ignoring overflow */
-    (S64)regs->GR_G(r1) *= (S64)n;
+    regs->GR_G(r1) = (S64)regs->GR_G(r1) * (S64)n;
 
 }
 
@@ -2588,7 +2588,7 @@ int     r1, r2;                         
     RRE(inst, execflag, regs, r1, r2);
 
     /* Multiply signed registers ignoring overflow */
-    (S64)regs->GR_G(r1) *= (S32)regs->GR_L(r2);
+    regs->GR_G(r1) = (S64)regs->GR_G(r1) * (S32)regs->GR_L(r2);
 
 }
 
@@ -2603,7 +2603,7 @@ int     r1, r2;                         
     RRE(inst, execflag, regs, r1, r2);
 
     /* Multiply signed registers ignoring overflow */
-    (S64)regs->GR_G(r1) *= (S64)regs->GR_G(r2);
+    regs->GR_G(r1) = (S64)regs->GR_G(r1) * (S64)regs->GR_G(r2);
 
 }
 
@@ -2620,7 +2620,7 @@ U16     i2;                             
     RI(inst, execflag, regs, r1, opcd, i2);
 
     /* Load operand into register */
-    (S64)regs->GR_G(r1) = (S16)i2;
+    regs->GR_G(r1) = (S64)(S16)i2;
 
 }
 
@@ -2662,7 +2662,7 @@ U16     i2;                             
     RI(inst, execflag, regs, r1, opcd, i2);
 
     /* Multiply register by operand ignoring overflow  */
-    (S64)regs->GR_G(r1) *= (S16)i2;
+    regs->GR_G(r1) = (S64)regs->GR_G(r1) * (S16)i2;
 
 }
 
@@ -2826,7 +2826,7 @@ int     r1, r2;                         
     RRE(inst, execflag, regs, r1, r2);
 
     /* Copy second operand to first operand */
-    (S64)regs->GR_G(r1) = (S32)regs->GR_L(r2);
+    regs->GR_G(r1) = (S64)(S32)regs->GR_L(r2);
 }
 
 
@@ -3349,7 +3349,7 @@ VADR    effective_addr2;                
     RXE(inst, execflag, regs, r1, b2, effective_addr2);
 
     /* Load R1 register from second operand */
-    (S64)regs->GR_G(r1) = (S32)ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
+    regs->GR_G(r1) = (S64) (S32)ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
 }
 
 
