[Iverilog-devel] Icarus Verilog snapshot 20130827
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Yep, I made a snapshot. The last time I made a snapshot is, according
to my git logs, December of 2012. That's been a while. And since this
is a snapshot of the master development branch, there is no way I can
come up with a usefully descriptive list of bug fixes. But here is a
list of grander points:

*) Big chunks of SystemVerilog support, including various complex
types, classes, packages, etc. Still a work in progress, but it
should be a quite useable subset by now.

*) Non-trivial chunks of VHDL (yes, VHDL) support. This is still
very much a work in progress, more a harbinger of things to come
then a useful tool at this point, but feedback is welcome.

*) Added a new BLIF code generator. (ASIC guys may know what this
means.) In the process, I've resuscitated some of the synthesis
support in the core compiler. This turned out to be easier then
I thought, so, to some degree, synthesis is back on the table.

*) Cary has put a lot of work into his vlog95 code generator, he's
been posting progress reports along the way.

*) Tons, and tons, and more tons of bug fixes, especially from
Cary and Martin, and others.

Of course, I suspect a lot of people who are interested in snapshots
are actually getting all of this by going directly to git, but it
seems to me enough has piled on to go to another snapshot. So have
at it!